Difference Between RISC and CISC

No.	RISC	CISC
1	It is an acronym for Reduced Instruction Set Computer. It is a type of microprocessor that has been designed to carry out few instructions at the same time.	CISC stands for Complex Instruction Set Computer. It is actually a CPU which is capable of executing many operations through a single instruction.
2	Faster than CISC	Slower than RISC chips when performing instructions
3	Pipelining can be implemented easily	Pipelining implementation is not easy
4	Direct addition is not possible	Direct addition between data in two memory locations. Ex.8085
5	Simple, single-cycle instructions that perform only basic Functions. Assembler instructions correspond to microcode instructions on CISC machine	A large and varied instruction set that includes simple, fast instructions for performing basic tasks, as well as complex, multi cycle Instructions that correspond to statements in an HLL.
6	RISC architecture is not widely used	At least 75% of the processor use CISC architecture
7	RISC chips require fewer transistors and cheaper to produce. Finally, it’s easier to write powerful optimized compilers	In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions.
8	RISC puts a greater burden on the software. Software developers need to write more lines for the same tasks	In CISC, software developers no need to write more lines for the same tasks
9	Mainly used for real time applications	Mainly used in normal PC’s, Workstations and servers
10	Large number of registers, most of which can be used as general purpose registers	CISC processors cannot have a large number of registers
11	RISC processor has a number of hardwired instruction	CISC processor executes microcode instructions
12	Uses Direct execution control unit.	Uses microcode control unit.
13	Price: move complexity from hardware to software.	Price: move complexity from software to hardware.
14	Performance: make tradeoffs in favor of a lower CPI, at the Expense of increased code size.	Performance: make tradeoffs in favor of decreased code size, at The expense of a higher CPI.