Direct Memory Access (DMA)
Data Transfer Technique, in which
data is transferred from memory to peripheral device without the involvement of
CPU, is called Direct Mode of Addressing or DMA. During this process CPU
remains idle and memory buses are under the control of DMA controller.
Whenever any device want to send
data through DMA it sends a DMA request to DMA controller. After Receiving the
DMA request from I/O Device DMA controller sends a Bus Grant (BG) signal to CPU
to take the control of buses. As CPU receives BG signal from DMA controller, it
terminates the execution of current instruction and places address bus, data
bus and rear write lines into high impedance state. This high impedance state
works as open circuit and output is disconnected.
Bus Grant (BG) signal is activated
by CPU in response to BR signal to inform DMA controller that buses are in high
impedance state and DMA controller can now take the control of buses.
DMA controller uses two techniques
for data transfer:
Direct Mode of Data Transfer(Burst Mode).
Cycle Stealing Mode of Data Transfer
Direct Mode of Data Transfer(Burst Mode).
Cycle Stealing Mode of Data Transfer
This Also Applicable to:
Introduction to DMA
Direct Memory Access(DMA)
Difference Between Burst mode and Cycle Stealing Mode of DMA
What is Cycle Stealing Mode of DMA?
What is Burst Mode of DMA?
Introduction to DMA
Direct Memory Access(DMA)
Difference Between Burst mode and Cycle Stealing Mode of DMA
What is Cycle Stealing Mode of DMA?
What is Burst Mode of DMA?
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